资源列表
timing_constraint
- 三速以太网时序约束参考设计，内涵quartus ii 工程，sdc文件-Triple-Speed Ethernet reference design timing constraints, content quartus ii project, sdc file
ASI
- 异步串行接口ASI,QUARTUS cv demo参考设计，实现ASI传输，完成8b/10b转换，串并转换-Asynchronous Serial Interface ASI, QUARTUS cv demo reference design, implementation ASI transmission, complete 8b/10b conversion, serial-parallel conversion
ASI_simulation
- 异步串行接口ASI仿真设计,quartus modelsim 仿真参考设计，实现ASI传输，完成8b/10b转换，串并转换-Asynchronous Serial Interface ASI simulation design, quartus modelsim simulation reference design, implementation ASI transmission, complete 8b/10b conversion, serial-parallel conversion
ahb_bus
- ahb总线代码,现支持4个master，可扩展-ahb bus verilog module
filtra-lowpass
- this a lowpass filtre in VHDL code with a test_bench you will find some specifications of the FIR-this is a lowpass filtre in VHDL code with a test_bench you will find some specifications of the FIR
CrossClockDomain
- 跨时钟域设计不错的设计，进过modelsim仿真通过。-Cross-clock domain design is good design been to modelsim simulation through.
sdr_ctrl_latest.tar
- SDRAM控制器设计源码，内含仿真代码，测试通过-SDRAM controller design source code, include simulation code, test by
1
- 基于FPGA的花样流水灯，实现多种8个LED多种方式流动的 verilog程序。-FPGA-based pattern water lights, LED achieve a variety of eight various ways flow verilog program.
PWM
- 用按钮控制PWM占空比，两个按钮调大调小，每次按键改变占空比1 。-Use the button to control the PWM duty cycle, two button adjusted, each button changes the duty cycle 1 .
xuanpin
- 用两个按键分别控制占空比的频率和占空比 8中频率 和四种占空比可调 可自己叫消抖，上机可用-Two buttons control the duty cycle frequency and duty cycle 8 adjustable frequency and duty cycle of four kinds can call themselves debounced on board available
anjianled
- 用按键控制流水灯一左移动亮起来，可自己修改成自己想要的型式-With a light water control buttons to move left lights up, you can make changes to the type you want to
Clock_div
- 偶数分频及50占空比输出，很详细，适合初学者-Even frequency division and duty cycle of the output 50, in great detail, suitable for beginners