资源列表
c3
- 在FPGA实现的加法器实现的Veilog代码，应用软件为赛林思公司的ISE9.1-adder Veilog
ex
- 用HDPLD实现的高速并行乘法器，其输入为两个带符号位的4位二进制数- HDPLD implementation with high-speed parallel multiplier, the input symbols with two 4-bit binary number
pld
- 四字路*通灯管理器的设计（含波形输出）-Management of traffic lights at the junction word design (including waveform output)
rectangle
- 在屏幕上形成矩形的VHDL程序，感觉还可以。-Rectangle on the screen at the formation of the VHDL process can also be felt.
screen
- 读屏幕上亮点坐标的VHDL代码，共同学习。-Read the screen coordinates of the bright spots on VHDL code, a common study.
bus
- 显示总线扩展的_VHDL代码，大家共同学习。-Show that the expansion bus _VHDL code, a common study.
sum_ten
- 十位累加器,EDA,FPGA,DDS信号发生器的相位累加器,可用.-Accumulator 10, EDA, FPGA, DDS signal generator of the phase accumulator can be used.
check
- 用Verilog实现的序列检测器，可以检测出任意规定序列-Verilog implementation using the sequence detector
lbuff_mem
- 延时代码,可以用在ＦＰＧＡ数据流水处理，图象处理，滤波-delay code
autoseller
- 自动售饮料机。用vhdl变写的自动售物品的程序。-Beverage vending machine. Writing vhdl variable with automatic procedures for the sale of goods.
base_fir
- 使用verilog 写的FIR滤波器，里面并有matlab程序，是从altera官网下来的。。希望对大家游泳。-Use verilog to write the FIR filter, which have matlab and procedures, are down from the official website of the altera. . Everyone would like to swim.
VHDL_USERGUIDE
- 本书的主要的服务对象是熟悉硬件系统，而对软件的设计经验缺乏的工程师；叙述了VHDL的用法-This guide is intended for the engineer who is familiar with the principles of hardware design, but has little experience in designing with a language-based synthesis system. It describes the general c