资源列表
EP8_FTESR
- FPGA/系统设计/altera/康芯公司设计-FPGA/system design
bid_shift_reg
- VHDL语言编写，实现双向移位寄存器功能，在MAX+plus软件下实现-VHDL language to achieve bi-directional shift register function MAX+ Plus software to achieve
j
- vhdl编程 实现移位寄存器。左移和右移-VHDL programming shift register. The left and shifted to right
clock
- 基于FPGA的数字时钟设计,本人试过，能用。-FPGA clock
VGA
- 这里有很全的ＶＧＡ的实例，对VGA具有很详细的讲解和编程，主要是Verilog语言进行编写。-Here are examples of very wide VGA for VGA has a very detailed explanation and programming, mainly written in Verilog language.
RTC
- Verilog语言编写的IIC读取RTC实时时钟程序(real time clock based on FPGA)
cpld
- 学习cpld的入门讨论资料 对新手还是有帮助的-an entry material to learn CPLD,it s good to the beginner of CPLD
cpld
- 给你一个易懂而生动的cpld开发介绍 让你可以直观的了解cpld开发的简单过程-Give you a straightforward and vivid descr iption cpld development so that you can develop an intuitive understanding of a simple process cpld
zhong5
- Basys2开发板上烧写后，可在LCD1602显示屏上动态显示年月日时分秒和温度值，并且可以手动设置闹钟和温度上下限，越限报警。(Basys2 development board programmer, can dynamically display the date when the minutes and seconds and temperature on the LCD1602 screen, and you can manually set the alarm clock and th
easy-CPLD
- 学习CPLD/FPGA很好的电子书．讲得很好．-Learning CPLD/FPGA good books. Put it very well.
Zynq-7000-for-Hardware-Engineers
- Zynq-7000硬件工程师step by step教程-Zynq-7000 Extensible Processing Platform Design Workshop for Hardware Engineers