资源列表
da_fir
- 分布式fir的实现 有源程序 可以自己修改 实现自己描述的功能-Implementation of a source distributed fir can modify the function to achieve their descr iption
VHDL_FINAL
- 附檔有詳盡的源碼與輸入輸出說明，包含模擬圖形與流程圖-Attached file has a detailed descr iption of source code and input and output, including analog graphics and flow charts
VerilogHDL
- 《设计与验证：VerilogHDL》的配套源代码，有丰富的例子，有利于初学者使用-Design and Verification: Verilog HDL "supporting source code, a wealth of examples, for beginners
calibre_drc_lvs_data_2006.3.tar
- Calibre DRC and LVS labs.
juzhenjianpan
- 基于FPGA，在quartus上，用WHDL语言和原理图设计的矩阵键盘显示电路。完整项目。-Based on FPGA, quartus, with WHDL language and principles of map design matrix keyboard display circuit. Complete the project.
UART_FIFO
- 用VHDL语言实现内置FIFO的UART，并做时序仿真和功能仿真确定正确与否。-Implement a built in FIFO UART using VHDL language, and do functional simulation and timing simulation to determine correct.
AHB_to_Wishbone_Verilog
- 该源代码包是AHB总线到Wishbone总线的交接器，包括以下4个部分：RTL源代码，测试平台，软件测试程序，说明文档。-This source package is the AHB bus to Wishbone bus bridge(wrapper).It has the following 4 parts: RTL codes, testbench, software simulating files, help documents.
dct_at_vlsi
- 有用_二维离散余弦变换的VLSI实现及IP软核设计
Controller
- Bidirection Counter for an Motor control application
BYSJM_VHDL
- 基于fpga实现的出租车计价程序，实现功能：通过DE2板上的数码管、LCD显示当前的里程数，实现低速计价等功能-Based fpga the Taximeter program to achieve, achieve function: the DE2 board digital tube, LCD displays the current mileage, low speed denominated functions
UBlaster
- USB Blaster full production data
Two_Port_RAM
- FPGA libero环境下 介绍ProASIC3/E的TWO Port RAM的使用-FPGA libero circumstances described ProASIC3/E use of TWO Port RAM