资源列表
SVA-script
- 一个自己总结的systemverilog assertion读书笔记，基本上systemverilog assertion的语法比较全。简单易懂。适合SVA入门。-systemverilog assertion scr ipt
rx_module
- 接收机的顶层模块构建,对需要参考的朋友有一定的帮助(The construction of the top module of the receiver is helpful to friends who need reference.)
61EDA_C2293
- 《设计与验证Verilog程序》书中的全部代码，很全-" Verilog Design and Verification procedures" all the code book, it is full
FFT
- 使用内嵌M3核的FPGA实现FFT的开发-embed the M3 s FPGA for FFT
Nexys_sch
- annother FPGA ucLinux Board reference design, using Xilinx s Spartan3 FPGA (XC3S400)
DDS_signal_genarator
- 这是一个利用verilog语言编写的信号发生器的例子，值得参考-this is a code about signal generator by VIERILOG LANGUAGE!
vhdlClock
- VHDL编写的电子时钟程序，经仿真正确，包含源码-Electronic clock program written in VHDL, the simulation is correct, including source code
NIOS_uCGUI
- NIOS_uCGU VHDL/FPGA/Verilog sopc- NIOS_uCGU VHDL/FPGA/Verilog sopc
vmodcam-ref-hd-demo-12
- 通过fpga控制从vmodcam中获取视频数据并通过vhdmi发送到显示屏上-And sent via fpga control access to video data from vmodcam on display through vhdmi
Verilog_Digital_System_Design
- Verilog digital System design 2007 second edition
zhengxianbo
- 正弦波发生器，基于verilog语言编写的，不用用DAC模块，直接输出0和1电频，经过RC滤波后就可得到波形-Sine wave generator, based on verilog language, do not use the DAC module, direct output power frequency 0 and 1, RC-filtered waveform obtained after
Verilog-digital-system-design-RTL-synthesis-testb
- verilog book. RTL sysnthesis testbech