资源列表
xapp851
- The xapp851.zip archive includes the following subdirectories. The specific contents of each subdirectory below: \rtl - HDL design files \sim - simulation files \synth - Synthesis related files \par - Place/Route related files-The xapp
ide_control
- 三段式Verilog的IDE程序，但只有DMA部分，需要自己添加PIO的代码-Verilog three-step procedure of the IDE, but only parts of DMA, PIO required to add their own code
flash
- flashing led example code
freqm
- frequency multiplier
jc2_vhd
- jhonson counter using shifter
hex2rom_0241_Win32
- This SPI-mode SD Card controller is a free SOPC Builder component that can be used in any SOPC Builder system. The included example design runs on the Nios II Embedded Evaluation Kit, Cyclone III edition (NEEK).-This SPI-mode SD Card controller is a
test1
- 4位数字频率计的verilog HDL设计，精度比较准的-4-digit Cymometer verilog HDL design, the accuracy of the quasi-comparison
testt2
- 由单片机和CPLD共同构成7位数字频率计-By the MCU and CPLD together seven digital frequency meter
8080cpu
- this code for cpu 8080 design -this is code for cpu 8080 design
lcd
- 用sopc技术实现对128*64的lcd液晶显示。这里是它的程序。 -Sopc technology used for implementation of 128* 64 LCD lcd. Here is the procedure.
sin_sample_clock
- EP2C CYCONLY 系列的FPGA时钟测试程序，是由内部时钟分频后，点亮数码显示灯来证明的。绝对好用的程序。编写的执行效率很高-EP2C CYCONLY series FPGA clock test procedure is determined by the internal clock frequency, the lamp lit digital display to prove. Absolute-to-use program. The preparation of the imp
serial_uart_top_new
- FPGA Cycloneii 系列的，测试串口通信程序，编程语言简洁，串口速率是115200bps，测试后好用的-Series FPGA Cycloneii to test the serial communication program, the programming language is simple and serial rates are 115200bps, easy-to-use test