资源列表
adder
- 高达16位加法器的实现，工作环境在ISE，modesim，该例程较为详细！-Up to 16-bit adder implementation, the working environment at ISE, modesim, the more detailed routines!
lcd_verilog
- 利用verilogＨＤＬ语言实现ＬＣＤ的驱动编程-Use of language implementation verilogHDL drive LCD programming
nptel-cad1-02
- Verilog notes - Part 2 from IIT M-Verilog notes- Part 2 from IIT M
nptel-cad1-04
- Verilog notes - Part 4 from IIT M-Verilog notes- Part 4 from IIT M
freq_high2low
- 输入一个高频时钟，输出一个频率可设置的周期信号的verlog模块，在系统设计时很方便-Enter a high-frequency clock, the output frequency can be set up a periodic signal verlog modules, system design at a very convenient
add
- 4位全加器设计，包含半加器构成全加器，由全加器构成4位全加器及其拓展-4bits
CordicNCO
- 基于CORDIC算法的，数字控制振荡器的设计。带测试程序，输入一个振荡频率，输出SIN和COS的波形！-Based on the CORDIC algorithm, the digital controlled oscillator design. With test procedures, enter a oscillation frequency, the output waveform SIN and COS!
BUFG_CLK2X_FB_SUBM
- xilinx DCM 应用的源代码，完全可用-xilinx DCM application source code, fully available
BUFG_CLK0_FB_SUBM
- xilinx DCM 应用程序，完全可用-xilinx DCM applications, fully available
BUFG_CLK0_SUBM
- xilinx DCM 应用程序，完全可用-xilinx DCM applications, fully available
BUFG_CLK2X_SUBM
- xilinx DCM 应用程序，完全可用-xilinx DCM applications, fully available
BUFG_CLKDV_SUBM
- xilinx DCM 应用程序，完全可用-xilinx DCM applications, fully available