资源列表
MAC_4_CSA
- MAC-4bit verilog source code with CSA style
IP_adder-8bit
- IP core of adder,8-bit width, three design concerpts with different effect.-IP core of adder ,8-bit width, three design concerpts with different effect.
fenping
- 介绍了各种分频器的设计，VHDL描述。包括偶数分频器，奇数分频器，办整数分频器-Introduce the design of a variety of crossovers, VHDL descr iption. Including even-numbered divider, prescaler odd, do integer divider
VHDL
- VHDL Programming by Example（McGraw.Hill著）经典国外教程，希望大家喜欢-VHDL Programming by Example (McGraw.Hill a) foreign classics tutorial, I hope everyone likes
AVR_Core
- AVR单片机的VHDL描述，希望对大家有所帮助-AVR microcontroller VHDL descr iption, and they hope to help everyone
video_compression
- 用VHDL实现的视频压缩算法，希望大家学习学习-Using VHDL implementation of video compression algorithms, study study hope that everyone
pwm_control
- 用VHDL实现的对电机的控制，包括正反转和调速-VHDL implementation of the use of motor control, including the positive and Speed
17869348VHDL
- 很多VHDL实力，大家好好看看 很好的 -二
add
- vhdl的最简单的加法器，quarters2编译通过-The most simple vhdl adder, quarters2 compiled through
bianma
- 基于VHDL设计的在quarters2上的循环码编码器-VHDL-based design at quarters2 on the cyclic code encoder
second
- 基于FPGA的秒表设计 基于FPGA的秒表设计-FPGA-based FPGA design is based on the stopwatch stopwatch stopwatch design FPGA-based design
crc_16
- 基于FPGA的1CRC_16校验 基于FPGA的1CRC_16校验-FPGA-based FPGA-based 1CRC_16 check 1CRC_16 check FPGA-based validation 1CRC_16