资源列表
cordic.rar
- 基于cordic算法的正余弦信号发生器，通过编译仿真,Cordic algorithm is based on the cosine signal generator, through the compiled simulation
ks0108
- This on source file of Glcd tat support farsi language-This is on source file of Glcd tat support farsi language
1
- 这是一个加法器，可以用来计算多位的加法运算。有需要的可以自己下载。-This is an adder, can be used to calculate the number of addition operations. Needs to download.
rxtx
- 简单的 RX TX串口发送接收模块 方便移植-Simple RX TX serial port to send and receive modules to facilitate transplantation
safe_state_machine_v
- The Verilog HDL Templates for State Machines that included in the Design Example web page are: o 4-State Mealy State Machine o 4-State Moore State Machine o Safe State Machine o User-Encoded State Machine-The Verilog HDL Templates for S
byvhdstopwatchl
- 1.高精度数字秒表（0.01秒的vhdl语言实现） 2.具有定时，暂停，按键随机存储，翻页回放功能； 3.对30M时钟分频产生显示扫描时钟 4.精度高达0.01s,并且可以通过改变主频来更改分频比和记数间隔，可控性高。 5.模块化设计，其中的许多函数可以成为vhdl语言的通用经典例子（包含分频电路设计，动态扫描时钟设计，译码电路设计，存储器设计，存储回放显示设计）-1. High-precision digital stopwatch (0.01 seconds vhdl la
AD7754_Spi_Change
- AD7754 configuring programming for energy meter
sramduxie
- sram的读写代码 并能送屏显示，能实现屏与sram的对应关系-The reading and writing code sram and can send screen, can realize the screen and the corresponding relation of sram
decoder_3_8
- 对于初学FPGA者，需要掌握各种编码、译码，这里给出3-8译码的VHDL设计代码。-For the beginner to the FPGA, need to master all kinds of coding, decoding, presented here 3-8 decoding VHDL design code.
Serial_LED_Interface
- This module implements the logic for controlling port LED based on link status received switch-This module implements the logic for controlling port LED based on link status received switch
clock
- verilog写的时钟程序，带有校时和闹铃功能-clock program written with verilog
vhdl
- 用VHDL实现加法 使用最小的计算时间以及最小的运算空间-Addition to the minimum computation time and minimal operator space using VHDL