资源列表
bfm
- Verilog HDL编写的总线功能模型，十分有用，需要的下载-Verilog HDL prepared by the bus functional model is useful, it needs to download
ourdev_461286
- 时钟分频器源代码，使用在fpga中，直接可以使用的源代码-Clock divider source code, used in the fpga, direct source code can be used
FSM-verilog
- 自己写的 FSM verilog代码 ，参考The Verilog Hardware Descr iption Languag-an example of Fsm written with verilog
dflipflop
- d flipflop for verilog code
crc
- crc32的 vhdl实现源代码，对crc原理有说明-crc32 to achieve the vhdl source code, has made it clear that the principle of the crc
D
- bit append16 VHDL source code
NIOS_Key
- 基于NIOS的键盘扫描代码。本例用查询方式实现！-NIOS-based keyboard scan code. Be achieved with the query in this case!
play-a-song
- 通过VHDL编程，控制下位机播放歌曲梁祝。-Through the VHDL program, under the control of the crew playing the song Butterfly.
42cb47db-de04-443e-ac41-d950bce5756a
- vhdl uart代码，自己调试用的，大家指点，支持一下-vhdl uart
Ch6
- 《Verilog HDL数字系统设计及仿真》第六章Verilog HDL测试模块源代码-" Verilog HDL design and simulation of digital systems," Chapter VI test module Verilog HDL source code
20FIRFilterDecimal
- 20阶FIR数字滤波器，参数没有进行倍数扩大，参数经过CSD编码处理-20-order FIR digital filter, the parameter no multiple expansion, parameter encoding process after CSD