资源列表
PWMAvalonExample
- PWM generation,Altera standard function.
adc8888
- 8位的a/d行为模型，可以应用于modelsim等环境下的仿真，不可综合。-eight of the a / d behavior model can be applied to other environments modelsim the simulation, not comprehensive.
gtx_drp
- 高速串行设计FPGA-GTX IP设置生成drp模块，可动态配置速率2.4Gbps，1.2Gbps，0.6Gbps，自适应链接-High-speed serial design FPGA-GTX IP setting generation drp module, dynamically configurable rate 2.4Gbps, 1.2Gbps, 0.6Gbps, adaptive link
gh_CORDIC_rotation
- This my version of the block, performing the functions of the quadrature oscillator-This is my version of the block, performing the functions of the quadrature oscillator
RA
- ripple adder 程式撰寫,此利用verilog撰寫-ripple adder
Rader17.v
- DFT Implementation with Rader Algorithm. 17 points DFT verilog implementation design.
FFT16
- 实现fft快速傅里叶变换，可以根据需要来进行修改。-Implementation fft Fast Fourier Transform, can be required to be amended.
eetop[1].cn_axibusregslice
- axi总线读写通道插入一级寄存器模块verilog源码,已验证- a slave interface is simple to achieve, need to look at
Shifters_vhdl
- -- Title : Barrel Shifter (Pure combinational) -- This VHDL design file is an open design you can redistribute it and/or -- modify it and/or implement it after contacting the author -- You can check the draft license at --- Title : Barrel Shift
spart6_usb_rw_example
- 这是USB芯片CY68013和FPGA互连的读写的实例代码，sparten6是新的FPGA平台，对需要使用新的平台的朋友，有一定的帮助。-This is the USB chip and the FPGA interconnect CY68013 read the example code, sparten6 a new FPGA platform, the platform on the need to use the new friends, have some help.
16FFT
- 基于FPGA的16点FFT实现VEILOG-FPGA 16FFT VERILOG
DLF
- 可增可减的计数器，可以用于全数字锁相环中的环路低通滤波器-Either upwards or downwards counter low-pass filter can be used for all-digital phase-locked loop in the loop