资源列表
uart_all
- verilog 的UART发送接收实验的实现代码-The realization of UART (verilog)
DDS
- 基于直接序列合成的vhdl语言 基于直接序列合成的vhdl语言-Synthesis based on direct sequence vhdl language synthesis based on direct sequence vhdl language synthesis based on direct sequence vhdl language
haming
- 基于VHDL的FPGA通信工程汉明编码方式的实现，并且有图形表示法生成的源程序-VHDL for FPGA realization Communication Engineering 程汉明 based coding, and generate a graphical representation of the source
Serial-comunication
- 基于VHDL的FPGA上实现串口通信的功能，本例为串口发送的源程序-Realize the function of serial communication based on VHDL-FPGA, in this case, the serial transmission source
SLX_3_REC_TEST
- 基于vhdl的FPGA上实现串口通信的功能，本例为串口接受功能-Based on the realization of serial communication function vhdl the FPGA, in this case, the serial acceptance function
FPGA
- 参加竞赛的FPGA双目测距的源码，包含上位机源码-Contest the FPGA binocular ranging source, including PC Source
uart_verilog
- 用verilog实现串口通信，实现串口的接收及发送。-Using Verilog serial communication, the realization of sending and receiving serial.
mul16
- 16位二进制数移位乘法器的实现,使用Verilog HDL实现-The realization of the 16 bit binary number shifting multiplier, use Verilog HDL to implement
clock2
- 基于Verilog HDL及DE2开发板的数字钟设计，使用Verilog HDL实现-Based on Verilog HDL and DE2 development board of the digital clock design, use Verilog HDL to implement
HDB3-encoderauncoder
- HDB3编码器与解码器，以及RTL图，使用Verilog HDL实现-HDB3 encoder and decoder, and RTL diagram, use Verilog HDL to implement
ADS1278
- 这个程序实现AD采样芯片1278与FPGA的通信，按照datasheet上的时序编写。-This program implements 1278 AD sampling chip and FPGA communication, written in accordance with the timing on the datasheet.
ManchesterCode
- 改程序将实现对两个信号的曼切斯特编码，以用仿真软件验证过了-Reform program will achieve two Manchester encoded signal to a validated using simulation software