资源列表
5956446verilog_ppt
- 具体介绍VHDL的原理，附带相关的例程。欢迎大家收藏下载-Introduced the principle of specific VHDL, incidental related routines. Welcome to the collection download
zzx
- 这个并串转换代码是依靠同步状态机来实现其控制的。其实并串转换在实际的电路中使用还是比较多的，尤其在通信线路方面的复用和分解方面，原理上就是一个串并转换和并串转换的过程。举个简单的例子，计算机串口发送数据的过程，如果满足发送条件了，其实就是一个并串转换的过程了。好了，废话不说，看代码就是。 写完一看，一个并串转换居然搞了这么大，有点失败。但是整个代码已经通过了后仿真，而且思路还是比较清楚的，可靠性和稳定性方面也应该没有问题滴，呵呵。不过说老实话，里面有些信号是确实可以去掉的，不过后来就懒
addsub_28
- 一种用VHDL语言描述的加减算法的源代码编程-A VHDL language to describe the addition and subtraction algorithm source code programming
pre_norm_sqrt
- 一种用VHDL语言描述的浮点平方根前规格化的源代码编程-VHDL language used to describe a floating-point square root of the source code before the standardized programming
pre_norm_div
- 一种用VHDL语言描述的浮点除前规格化的源代码编程-VHDL language used to describe a floating-point addition to the source code before the standardized programming
pre_norm_mul
- 一种用VHDL语言描述的浮点乘前规格化的源代码编程-VHDL language used to describe a floating-point by the source code before the standardized programming
pre_norm_addsub
- 一种用VHDL语言描述的浮点前规格化的源代码编程-VHDL language used to describe a floating-point before the standardized programming source code
exp11
- lcd实验的.c源文件，经验证，已经完全正确了。-lcd experiment. c source file, experience certificate, has been completely correct.
exp11
- lcd实验的.h文件，经验证，已经完全正确的了。-lcd experiment. h file, experience certificate, has been completely correct.
clock
- 用高速硬件语言VHDL设计的全功能数字钟，经测试运行稳定-VHDL language used high-speed hardware design full-function digital clock, tested and stable operation
Pentium
- 这两个分别是8位乘法器的VHDL语言的实现，并经过个人用QUARTUS的验证，另外一个是奔腾处理器的设计思想-The two were 8 multiplier realization of VHDL language and personal use Quartus After verification, another is a Pentium processor design idea
Verilog130examples
- 这是一个130个vhdl代码的实例，其中说明都在压缩包里面的-This is a 130 VHDL code examples, which described in the cabinet inside