资源列表
THXS3EI-I_student_final
- tinghua FPGA ziliao -tinghua FPGA ziliao
I2C
- 基于FPGA的I2C总线主控器的设计与实现-Based on the I2C bus master FPGA Design and Implementation
forVerilog_HDLbeginner
- 很好的入门级verilog教程。 有很多实例，可供参考。-Very good entry-level Verilog Tutorial. There are many examples for reference.
AUTOLED
- 共6个尾灯，汽车正常行驶时，6个灯全灭； 左转时，左边3个灯从右到左依次亮灭； 右转时，右边3个灯从左到右依次亮灭； 刹车时，车灯全亮；故障时，全部闪烁。 在软件工具平台上，进行VHDL语言的各模块编程输入、编译实现和仿真验证。 -A total of six taillights, car normal driving, the six light body turn left when the left 3 lights from right to left follo
timer
- 能够实现小时（24进制）、分钟和秒钟（60进制）的计数功能 具有复位功能 功能扩展：具有整点报时提示、定时闹钟等功能 -To achieve an hour (24 hexadecimal), minutes and seconds (60 hexadecimal) count function function reset function expansion: with the whole point timekeeping tips, regular features such
display_control
- 一个LCD控制器的verilog源代码，可以方便的控制TFT LCD！-An LCD controller Verilog source code, can easily control TFT LCD!
vhdl
- 要求用VHDL语言设计7人表决器和系列检测器，检测“1111111101111110”-VHDL language design requires a vote 7 and Series detector 1111111101111110
dzq
- 利用数控分频器设计硬件电子琴.硬件电子琴电路模块设计-Use hardware organ NC divider design. Hardware electric circuit module design
mp3_decoder
- MP3解码的VHDL实现，包括霍夫曼解码等-VHDL realization of MP3 decoding, including Huffman decoding
ring
- 用于打铃系统的vhdl实现的源码，是一个很好的教学代码！-Bell system for playing the realization of VHDL source code, is a very good teaching code!
display
- vhdl实现的显示模块的源代码，是电子竞赛的必备源码-VHDL realization of the display module s source code, is an essential source of electronic competition
clock
- 时钟的vhdl实现，具有打铃等功能，是一个很好的实现，我们做电子竞赛的源代码-VHDL clock to achieve a play-ling and other functions, is a good realization, we have the source code of the electronic competition