资源列表
RS232_pro
- RS232 verilog coding 全参数化设计 可以自己设定波特率 时钟频率等 完全FPGA实现调通-RS232 verilog coding the entire parametric design can set the baud rate clock frequency of FPGA to achieve complete transfer pass
Traffic_Light
- 在XILINX环境下，实现交通信号灯控制，VHDL语言编写。-In the XILINX environment, the achievement of traffic signal control, VHDL language.
100Examples
- verilog 语言 可以免费下载的程序-Verilog language can be downloaded for free procedures
eda
- 关于EDA编程的一些程序，绝对好 用！精典-EDA programming on some of the procedures, the absolute ease of use! Classical
FPGA
- cycloneII的详细手册资料包括handbook，封装-cycloneII detailed information including manual handbook, Packaging
dianziqingVHDL
- 简易电子琴 基本代码，不完全，希望有人能补充 -Simple flower basic code, not completely, I hope someone can add
spi
- spi的FPGA驱动 用于嵌入式开发系统-spi the FPGA-driven development for embedded systems
baskterballconter
- 这是一个关于篮球24秒计数的Verilog程序，程序中包含了开始，暂停，复位键。-This is a matter of 24 seconds count basketball Verilog procedures, the procedures included in the start, pause, reset button.
csa_float_multiplier
- 新型的浮点乘法器 用csa来实现可以用在浮点乘法器的地方-A new type of floating-point multiplier with CSA to achieve floating-point multiplier can be used in place
std_cf_2s60_ES
- Altera公司开发板2s60 CF卡通用例程（初始化、读、写、测试等）-Altera Corporation development board 2s60 CF Card routines (initialization, read, write, test, etc.)
QuartusII
- QuartusII软件培训教程，介绍了QuartusII的一些基础知识，供初学者参考！-QuartusII software training tutorials QuartusII introduced some basic knowledge, the reference for beginners!
post_norm_addsub
- 浮点加减运算的后规格化VHDL程序源代码，很不错，希望对大家有用-Floating-point addition and subtraction operations after the standardized VHDL source code, it is good, I hope all of you a useful