资源列表
VHDLplj
- (1)设计4位十进制频率计测量范围: 1Hz～9999Hz (2）测量的数值通过4个数码管显示 (3）频率超过9999Hz时，溢出指示灯亮，可以作为扩大测量范围的接口-(1) the design of four decimal frequency measuring range: 1Hz ~ 9999Hz (2) measurement values through four digital tube display (3) the frequency of more than 999
VHDL
- VHDl在FPGA上实现浮点运算，给初学者使用-VHDL in FPGA to achieve floating-point operations for beginners
VHDL-Cookbook
- 全面详细介绍了VHDL，英文版，作者Peter.J.Ashenden-Full details of VHDL, the English version, the author Peter.J.Ashenden
divide
- Verilog hdl语言的常用除法器设计，可使用modelsim进行仿真-Commonly used languages Verilog hdl divider design, can use the ModelSim simulation
GFmultiply
- Verilog hdl语言 伽罗华域GF（q）乘法器设计，可使用modelsim进行仿真-Language Verilog hdl Galois field GF (q) multiplier design, can use the ModelSim simulation
add
- Verilog hdl语言 常用加法器设计，可使用modelsim进行仿真-Verilog hdl language commonly used adder design, can use the ModelSim simulation
S8_VGA
- VGA的verilog hdl 程序，完成显示长条状显示不同颜色-VGA s verilog hdl procedures, completion of a long strip show show different color
NcVerilog_tutorial
- nc verilog 的使用说明和实例，对于实用nc来进行仿真进行了详细说明。-nc verilog instructions and examples for the utility to carry out simulation nc described in detail.
classic_Verilog_135_examples
- Verilog的135个经典设计实例。包含源码和说明-Verilog of 135 examples of classic design. Contains the source and descr iption
schk
- 实现8位数据的输入检测功能，如与预先输入的数字相同则输出A，否则输出B-To achieve 8-bit data input detection function, such as with the pre-enter the same number as output A, or output B
half_adder
- 实现一位加法器的设计，假设输入参数为A,B，则输出为A,B的和-The realization of an adder design, the assumption that the input parameters for the A, B, the output of A, B and
chengfaqi4
- 用VHDL实现四位乘法器，不直接用乘法实现，一来节省资源，二来可提高速度！-Use VHDL to achieve four multiplier, not the realization of the direct use of multiplication, one to save resources, and secondly to improve the speed!