资源列表
02_VHDL_program`structure
- 这个是关于vhdl的程序语言结构的ppt,很哈的啊，好不容易从老师那讨来的-This is the procedure on the VHDL language structure ppt, Kazakhstan ah very hard to learn from their teachers to discuss it
adder4
- 是用verilog写得加法器以及计数器里面有测试文件（testbench），对于初学者来说这个可以用来参考下-Is written in Verilog adder and counter inside a test file (testbench), for beginners this can be used to reference the next
VerilogDHL_clock
- 新来匝道穿上别人写的基于vhd的数字时钟很好大家看看啊，很规范的哦。-New ramp to wear someone else wrote vhd on the digital clock very well take a look at the ah, oh, very norms.
i2cverilog
- 采用verilogHDL编写的I2C接口及SPI接口模块，经过测试 相当不错 COPY过去可直接使用-VerilogHDL prepared using I2C interface and SPI interface module, tested pretty good the past can be directly used COPY
VHDL
- 1 8位加法器的设计 2 分频电路 3 数字秒表的设计-1 8 adder design of 2-circuit design of 3 digital stopwatch
Verilog_VGA
- 一个是用Verilog的程序 还可以用 -One is to use Verilog procedures also can be used
song
- 音乐，梁祝，其中应用VHDL编写的全过程梁祝。-Music, Butterfly Lovers, in which the application of VHDL to prepare the whole process of Butterfly Lovers.
digital_clk
- 该工程的主要功能是由VHDL语言实现多功能数字电子时钟-The project s main function is to achieve by the VHDL language multifunction digital electronic clock
MODELSIM
- 2008自由电子FPGA开发板介绍MODELSIM经典教程-2008 free-electron FPGA development board, introduced the classic ModelSim Tutorial
verilog_language
- Verilog学习全部资料，学习的同志赶快收了-Verilog learning all the information, learning comrades as soon as possible upon receipt of a
Verilog_for_study
- Verilog黄金参考指南，硬件学习必备的知识！-Verilog Golden Reference Guide, hardware learning essential knowledge!
Verilog-book
- 学习Verilog语言必备资料，包括语法总结 编写Verilog HDL 源代码的标准及设计流程-Verilog language learning essential information, including syntax summary of Verilog HDL source code for the preparation of standards and design process