资源列表
ADF4113_loader
- ADF4113 loader written on Verilog + Icarus Verilog testbench
adder
- float_adder and multiplier.
decoder38
- 38译码器源码VHDL版， cpld EPM570版-38 decoder VHDL source code version
piso8_ok
- 串并转换，VHDL版，epm570t100c芯片-Serial to parallel conversion, VHDL version, epm570t100c chip
syn_cnter_4
- 四位计数器，VHDL版，基于cpld EPM570芯片-The four bit counter, VHDL version, EPM570 chip based on CPLD
example16-dac7512-sina-wave-ok
- VHDL 基于cpld EPM570的DA转换代码-VHDL CPLD EPM570 the DA conversion code based on
pro
- 基于Verilog HDL的数字交通灯的设计-Digital Verilog HDL-based design of traffic lights
usb_packet_fifo
- usb packet fifo VHDL
tx_buffer_inband
- FPGA,TX发送模块VHDL程序。-tx buffer inband VHDL
Verilog135
- VERILOG实用小例，约135个，特别对于初学者很有用处-VERILOG Practical cases, about 135, particularly useful for beginners
counter
- 一个100MHZ的时钟信号经过分频器得到1HZ信号，然后输入到三位计数器中，计数器的输出在相应的FPGA上的LED灯上展示。该程序主要包含四部分：测试文件、顶层文件、分屏器模块和计数器模块。-100MHZ clock signal through a divider to get 1HZ signal, and then input to the three counters, the output of the counter displayed on the corresponding LE
simple_CPU_VHDL
- 简单的CPU的VHDL设计 vhdl代码和cpu设计过程--Simple CPU design of the VHDL code and VHDL design process cpu