资源列表
Traffic-Controller
- 本代码为基于Spartan6的verilog交通控制灯代码，在ISE软件中仿真成功。-The code for the verilog code Spartan6 traffic control lights on in the ISE software emulation success.
Adder
- 本代码为用三种方法实现verilog加法器代码，在ISE中基于Spartan6仿真成功。-This code is used three methods to achieve adder verilog code, based on the success in the ISE Spartan6 simulation.
labmic_soc
- SoC and FPGA desgin
mips
- 基于MIPS架构实现的单周期处理器，包含多种基本操作，验证方法是把自己的学号写进连续内存。-MIPS-based architecture for single-cycle processor, includes a variety of basic operations, authentication method is to learn their numbers written contiguous memory.
6UIO2
- 此程序为计算机开关量板卡的CPLD程序，仅供参考。-The program for the computer switch board and CPLD program, for reference only.
VGA_DATA
- Create VGA module using VHDL on Altera DE2. It is better if you understand the full theory of VGA.
DE2_115_Audio
- This a shared & storage file, which was written by Altera. It is quite possible that Applications will use this sample.-This is a shared & storage file, which was written by Altera. It is quite possible that Applications will use this sample.
DE2_115_TV
- This an application of FPGA which wrote by Altera. It can be used for interfacing VGA, SDRAM on DE2-115-This is an application of FPGA which wrote by Altera. It can be used for interfacing VGA, SDRAM on DE2-115
lcd1602
- 本程序是1602型LCD的字符显示程序，可以直接下载使用。-This program is a 1602-type LCD character display program, you can directly download.
double_closed_loop
- 本程序是基于zynq_7000的FPGA的一个同步电机控制的平台，verilog语言-based on zynq_7000 fpga-MOTOR CONTROL
RS-encoder
- RSC encoder in VHDL. Hope it helpful.
V2.tar
- SDIO slave, written in verilog, does not support SPI mode.