资源列表
APB_slave
- APB slave template for AMBA bus written in Verilog
or1200.tar
- OpenRISC 1200 cpu with integrated patches to support ORPSOC and FuseSOC builders
verilog-arbiter.tar
- Verilog arbitrator for Wishbone R3 compliant bus
wb_sdram_ctrl.tar
- Generic Wishbone R3 compliant SDRAM controller written in Verilog
bt656_to_yuv422
- 从bt656数据流中提取出同步信号, 适合于搞fpga/cpld开发调式-bt656 internel sync to extern sync singal， bt656 internel sync to extern sync singal
bt656_timing_analysis
- BT656信号分析参考规格书，对分析bt656信号非常有帮助-The video standard ITU-R.656 timing analysis
Basys2Lcd
- This the file of controling a LCD display of Basys2 board used to pass the exams of VHDL-This is the file of controling a LCD display of Basys2 board used to pass the exams of VHDL
pingpong
- 使用Verilog HDL 实现了一个桌球游戏，并在DE2开发板上验证通过。-Use Verilog HDL to achieve a table tennis game, and through the verification on the DE2 development board.
fpga-usb-verilog-test
- 红色飓风开发板中USB测试源码部分，包含说明文档，FPGA的verilog代码，cy68013固件程序，上位机测试程序。实现USB回环测试，可作为usb开发的参考文件-Red hurricane development board of the USB test source code, including documentation, FPGA verilog code, cy68013 firmware program, PC test program. Realization of USB
snaketc
- 贪吃蛇游戏机 用一个 8×8 点阵做为基本显示屏，4 个连续移动的的发光点表示一条蛇，用任意出现的一个亮点表示老鼠，用4 个排成一条线的发光点表示“墙”；用两位拨码开关控制蛇的运动方向，蛇撞“墙”、边或者游戏时间到，则游戏结束；老鼠出现的位置是随机的，每次出现的时间是5 秒钟，如果5 秒钟之内没有被吃掉，它就会在其它地方出现；用数码管显示得分情况和游戏剩余时间，每吃掉一次老鼠就加一分。 -Snake game console with a 88 dot matrix display as
fifo
- VHDL code for DATA PATH for performing A=A+3 and A=B+C TO DESIGN AND SIMULATE DATA PATH FOR PERFORMING A=A+3 AND A=B+C USING ONLY ONE ADDER.
led_demo
- 一个流水灯的实现程序，可以在此基础上进行修改。-The realization of a light water program can be modified based on this.