资源列表
Nexys4_Vivado_Basic
- DIGILENT Nexys4_Vivado_Basic.zip
NEW_DM9000
- FPGA实现DM9000驱动网卡通信,shijuxin开发板-Implementation DM9000 driver card communication，SJX Development Board
fifo_1
- 本程序是基于Xilinx的FPGA简单代码编写，对fifo的ip核进行简单的配置，并通过仿真代码进行仿真观察fifo的特性，适用于FPGA初学者。-This procedure is based on Xilinx' s FPGA simple code written for the ip nuclear fifo simple configuration, and Simulation observed through simulation code fifo for FPGA beg
sp605_BRD_rdf0033_13.2_c
- spartan605评估板测试代码。xilinx官方资料-spartan605 uation board test code
100-tips-for-FPGA-design
- 100 tips for FPGA deisgn
Verilog_HDL_Synthesis_A_Practical_Primer-Bhaskar-
- Verilog HDL Synthesis A Practical_Primer Bhaskar-1998
9G-informationof-FPGA
- 9G的FPGA学习资源,可以为你学习FPGA提供有效的方法-9G information of FPGA，these can help you learn FPGA effciently.
ep1c12_2_led_water
- 描述一个led灯的流水灯设计，可以检查晶振的好坏，检查最小系统是否正常工作-Describe a led lamp design, water can check the quality of the crystals check minimum system is working correctly
zzq
- 基于verilog实现VGA乒乓球游戏，实现VGA显示三维的乒乓球台，-Verilog oingoangball
sram_test_OK
- 主要是基于FPGA(EP2C8Q208I8)下的SRAM驱动，SRAM型号为IS61LV25616，程序语言为Verilog,开发环境为quartusII 7.0,为一工程，可直接下载到FPGA中，含电路图-Mainly based on FPGA (EP2C8Q208I8) driving under the SRAM, SRAM model IS61LV25616, programming language for Verilog, a development environment for
fsmc_ad9215
- 主要是基于FPGA(EP2C8Q208I8)下的高速AD9215驱动，程序语言为Verilog,开发环境为quartusII 7.0,为一工程，可直接下载到FPGA中，含电路图-Mainly based on the high-speed AD9215 FPGA (EP2C8Q208I8) under the driver, the programming language for Verilog, a development environment for quartusII 7.0, for
ViterbCoder217
- vertbi217编码的Verilog实现-vertbi217 coding verilog realization