资源列表
61_assign
- 基于同一基类型的两分辨类型的赋值相容问题6基于同一基类型的两分辨类型的赋值相容问题6-failed to translate
spi_eeprom_conf
- 实现spi接口的传输，并多外接EEPROM读写数据-Spi interface to achieve the transfer, and multiple external EEPROM read and write data
IIC1
- i2c verilog code for de2 board
USB_Interface
- verilog USB USB的slave fifo的控制-verilog USB
TLC549_ADC
- AD转换经过测试之后验证，能稳定输出采样数据，达到基本的设计要求和功能。-Tested verified after AD conversion, can stabilize the output sample data, designed to meet the basic requirements and capabilities.
tongxu
- VHDL通信程序 VHDL通信程序 VHDL通信程序-VHDL communication program
COUNT
- 设计一个最大分频为225的分频器，将50MHz时钟作为输入。分频器可以通过计数器来实现，通过一个25位的计数器，然后在最后一位输出，则产生了一个最大分频为225的分频器。-Design a maximum frequency divider 225, the 50MHz clock as input. Divider can be achieved through the counter, through a 25-bit counter, and then the last one out,
fdpll
- 简单的可配置dpll的VHDL代码。 用于时钟恢复后的相位抖动的滤波有很好的效果， 而且可以参数化配置pll的级数。-simple configurable dpll VHDL code. Clock Recovery for the jitter filtering is a very good result, but can pll configuration parameters of the series.
verilog-program
- 一些有用的FPGA程序，通过调试仿真，并在目标板上运行成功。-Some useful FPGA programming through debugging emulator and the target board to run successfully.
adc.v
- this an adc interface verilog code-this is an adc interface verilog code
GCD
- 最大公约数的计算,各个源描述的编译顺序:gcd.vhd,gcd_stim.vhd-The common denominator of the calculation, the various sources described in the order of the compiler: gcd.vhd, gcd_stim.vhd
adapt_filt_
- adaptive filter with two reference signal for filtering noise