资源列表
oob_control
- sata协议物理层的OOB带外信号控制实现的VHDL代码-the sata protocol physical layer OOB band signal control VHDL code
anolog_conversion.rar
- analog to digital data conversion using vhdl,analog to digital data conversion using vhdl
uart_receive5bytes
- C语言实现CPLD串口接受五个字节，有校验，检验无效不做处理，接续检测接受，注释详细。-C language CPLD five byte serial accept check, test invalid without processing, splice detection to accept detailed notes.
LMS
- 用verilog编写的lms算法。可实现自适应滤波功能-Lms algorithm written in verilog. Adaptive filtering can be achieved
TEST
- Xilinx ///Microblaze中添加手动LCDIP的测试程序-Xilinx///Microblaze to add manually LCDIP test program
vrom
- 任天堂nes系统，存储器部分代码，希望大家用得着-Nintendo nes system, the memory part of the code, I hope you need it
ADD_SUB
- floating point fused add-subtract unit
parity
- Eight bit Parity generator in verilog with Mux Generador de paridad de ocho bits con multiplexor
sdirx
- GV7601 GSPI驱动程序 配置GV7601 支持loopback环路输出 -GV7601 GV7601 GSPI driver configuration supports loopback loop output
pjt
- NIOS-II中PIO模拟的IIC驱动控制MT9M034摄像头-PIO simulated IIC driver control MT9M034 camera based on NIOS_II core
verilog-code-FOR-COMPARATOR--TFF-AND-BCD-TO-7SSD.
- // File : 4 Bit Comparator design using behavior modeling style.v-// File : 4 Bit Comparator design using behavior modeling style.v
arm
- 此程序是ARM+FPGA的总线通信程序，我只提供FPGA这一边的，其实我现在把这个程序移植到dsp+cpld上面去了，那个程序其实都出不多-This program is ARM+ FPGA bus communication procedures, I only FPGA side, in fact, I now put this program ported to dsp+ cpld go above, and that the program actually much