资源列表
UART_VHDL
- UART VHDL component
devider
- a divider design based on verilog language
yedek_son
- a basic Mode Decision hardware for Variable Block Size Motion Estimation in verilog
decoder
- coder for different modules in verilog
ddr_sig
- This VHDL or Verilog source code is intended as a design reference // which illustrates how these types of functions can be implemented. // It is the user s responsibility to verify their design for // consistency and functionality through the
iprecieve
- udp协议的ipreceive模块，用verilog写的，思路很明确-Udp agreement ipreceive module, written with verilog, the idea is clear
PWM256
- Verilog 所寫的可程式 PWM 信號產生器. 特點是設定參數時不會產生Glitch現象. 包含二個 .do 檔給 model*sim 幫助編譯及模擬.-A PWM generator writing in Verilog. This module will generate glitch while changing the setting. Including 2 .do files which can help compiling and simulating in the model
full_adder
- a full adder verilog source created by two half adder
1032yiwei_new
- CPLD LATTICE1032测试模式代码-CPLD LATTICE1032 test model code
WM8731_config
- FPGA的语音识别芯片WM8731，已在DE2板子上实测，可用。-FPGA speech recognition chip WM8731, have been measured in DE2 board, available.
Buffer
- parametrizable register and mux in VHDL of data rage, using std_logic_vector type
fifo_ip
- 定制fifo IP核，8位宽，256深度，实现数据的写入和读取-Custom fifo IP core, 8-bit wide, 256 deep, realize the writing and reading of data