资源列表
etd-0907106-180333
- VLSI DESIGN FOR WAVELET BASED SPEECH ENHANCEMENT SYSTEM
Labs
- verilog labs some helpfull basic taughts-verilog labs some helpfull basic taughts..
mix_project
- cordic , rotator projects in vhdl
16_sd_test
- SD卡相关FPGA程序VHDL源代码，可直接用！用ISE打开！-Sd card related FPGA program VHDL source code, can use directly!Using ISE open!
miaobiao
- vhdl实现秒表，功能包括计时、冻结时间显示、暂停-vhdl implementation stopwatch functions, including time, freezing time display, pause
s16_sdram
- VHDL 语言如何写SDRAM的源代码，很详细的-VHDL for SDRAM
FPGA_VHDL_
- 简易函数发生器,EDA课程设计，产生四种波形-four wave of function generation
BKMP3_verilog
- The mp3 decoder write by using Verilog
ad7691
- ad7691驱动文件，包含ip和源文件ad7691驱动文件，包含ip和源文件ad7691驱动文件，包含ip和源文件
UART
- 包含一个在QUARYUS环境下运行的UART的工程，实际在EP2C20Q240上调试成功的通用串口VHDL程序-The QUARYUS environment contains a UART to run the project, the actual success of the EP2C20Q240 Universal Serial debugging VHDL programs
CPU
- 包含CPU每部分器件的编写，通过改写RAM内容，可实现CPU简单运算的仿真-Some devices include the preparation of each CPU, RAM by rewriting the content, enabling easy operation simulation CPU
SDRAM_RaW
- 本实例用于控制开发板上面的SDRAM完成读写功能；先向SDRAM里面写数据，然后再将数据读出来做比较，如果不匹配就通过LED变亮显示出来，如果一致，LED就不亮。-This instance is used to control the development board to complete the above SDRAM read and write capabilities first SDRAM write data inside, and then compare the data