资源列表
BasedFPGAfloating-pointOperationByVHDL
- FPGA上浮点算法的实现，用VHDL语言编程-FPGA on the realization of floating-point arithmetic, using VHDL language programming
freq
- 智能频率计 1. 频率测量范围为1Hz~1MHz 2. 当频率在1KHz以下时采用测周方法 其它情 况采用测频方法.二者之间自动转换 3. 测量结果显示在数码管上,单位可以是Hz（Ｈ）、 KHz（ＡＨ）或MHz（ＢＨ）。 ４. 测量过程不显示数据，待测量结果结束后，直接显示结果。 -Intelligent frequency meter 1. Frequency measurement range of 1Hz ~ 1MHz 2. When th
VGA
- 基于FPGA嵌入式开发实现的VGA接口，已经验证通过。-FPGA-based embedded development to achieve the VGA interface, has been adopted to verify.
c23_RS_decoder
- 精通verilog HDL语言编程源码9——RS(204,188)译码器的设计-Proficient in verilog HDL source programming language 9- RS (204188) decoder design
c20_cordic_computer
- 精通verilog HDL语言编程源码之6--CORDIC数字计算机的设计-Proficient in language programming verilog HDL source of 6- CORDIC digital computer design
VHDLProgrammingbyExample
- VHDL启蒙书，我在国外读书的老师推荐的-VHDL enlightening book, I was studying abroad teachers recommended
c19_CICfilter
- 精通verilog HDL语言编程源码之5--CIC积分梳状滤波器设计-Proficient in verilog HDL source language programming of 5- CIC Integrator Comb Filter Design
c16_multiple
- 精通verilog HDL语言编程源码之2--常用乘法器设计-Proficient in verilog HDL source language programming of 2- Common Multiplier
c15_add
- 精通verilog HDL语言编程源码之1--常用加法器设计-Proficient in programming language source verilog HDL of 1- Common adder design
RC5_inv
- 不带state machine的decryption of rc5-State machine without the decryption of rc5
inverter
- rc5的decryption，同样带state machine，同样有四个状态-RC5 of decryption, with the same state machine, the same four state