资源列表
FPGAdesign
- 这是一个关于FPGA设计的高级进阶，介绍了一些设计技巧-This is a study on high-level Advanced FPGA design, introduced a number of design skills
modelsim
- 这是一个关于仿真工具MODELSIM的安装和使用。-This is a ModelSim simulation tool on the installation and use.
8051forxilinx
- 这是一个基于xilinx平台的8051处理器文件，用VHDL代码编写-This is a platform based on Xilinx 8051 processor document, using VHDL coding
vhdl-Jijin
- 关于VHDL语言的设计例子集锦，对于初学者来讲非常合适，可以对比自己的程序来找出更好的设计思路-On the VHDL design language allehanda example, in terms of very suitable for beginners, you can contrast their own process to identify a better design ideas
vhdldesign
- 这个课件主要讲 VHDL设计实体的结构 为学字子系统的同学提供帮助-The main speaker courseware structure of VHDL design entities to learn the words to help students subsystem
lift_syn
- 实现简易4层电梯控制核心模块，完成了电梯上下层控制、指示灯显示、优先级判断等多种常用功能。-The realization of simple 4 layer core elevator control module, the completion of the elevator on the lower control, indicator light shows that determine the priority and many other commonly used function
4bit_buma_adder
- Verilog作业 ：自己写的源码输入，补码输出的，由状态机控制的四位加法器，为保证时序，加法器模块为超前近位加法器，包含测试台，通过 Modelsim 、Synplify仿真。-Verilog operation: the source code to write their own input, complementary code output by the state machine to control the four adder, in order to ensure timing
jia
- 2FSK调制功能，欢迎下载使用。不用谢了-2FSK modulation function, welcomed the download. You re welcome a
DDR_SDRAM_controller
- DDR SDRAM控制器的VHDL源代码，含详细设计文档。 The DDR, DCM, and SelectI/O™ features in the Virtex™ -II architecture make it the perfect choice for implementing a controller of a Double Data Rate (DDR) SDRAM. The Digital Clock Manager (DCM) provides t
VHDLjiaotongdeng
- 有关毕业设计交通灯的ＶＨＤＬ设计，包括源码程序和仿真图形相关报告。-Traffic lights on the graduation project of VHDL design, including source code and simulation procedures related to the report graphics.
LOCK
- 基 于FPGA的电子密码所 设计,有详细的设计思路以及部分代码-FPGA-based electronic password by design, detailed design and some code
FIR_VHDL
- FIR滤波器的VHDL代码,可以修改冲击函数的值-FIR filter VHDL code can modify the impact of the value function