资源列表
hanming_HDL
- 汉明码编解码的两个例程，作为单元模块分别调入所开发系统-codec of two routines, as modules were transferred by the Development System
ledrom
- 流水灯的VHDL源代码。当设计文件加载到目标器件后，LED灯会按程序设定的规律进行闪烁。-Water lights VHDL source code. When the design document, after loading to the target device, LED lantern according to the procedure set by law of flicker.
PL_DPSK
- vhdl语言实现 dpsk调制以及解调 还有hdb3编码-vhdl language dpsk there hdb3 code modulation and demodulation
VerilogCode_time_of_day_clock
- Verilog Code for time-of-day clock and it is implemented on Altera DE2 board-Verilog Code for time-of-day clock and it is implemented on Altera DE2 board
dffasynchronous
- this ram both asynchronous and synchronous reset signals which is basic for any registers and basic memory element-this is ram both asynchronous and synchronous reset signals which is basic for any registers and basic memory element
MII_timing
- 用FPGA实现MII的数据传送时序控制,方法简单实用，设计及其精巧-implementation of MII data transmission’s timing control
slaveAHB
- amba总线的AHB部分，与从机相连接口的写法，载自其它网页。-amba AHB bus parts from the machine connected to the interface with the wording set out from other pages.
I2C
- I2C的Verilog HDL简单学习程序-The Verilog HDL simple I2C learning process
monitor
- driving monitor by xilinx xc2s200 fpga
dianti
- 在VHDL语言环境下实现6层楼的电梯控制系统-VHDL language environment in the realization of 6 floors of elevator control system
new_jilei15
- 脉冲累加器完成对15脉冲累加。用于雷达测距-inpuse add
basketballcounter
- a basketballscore counter two band 0--a basketballscore counter two band 0-999