资源列表
DSCH2
- VLSI compiler or nano chip designer.
lec_Chap2
- Verilog Hardware Descr iptive Language
source
- VHDL Altera example code
phase-locked-loop-implementation
- 在FM0数据解码时，利用锁相环生成数据同步时钟信号。文件为锁相环实现。Verilog HDL-When FM0 decoding data using the phase-locked loop generates the data synchronizing clock signal. File for phase-locked loop implementation.Verilog HDL
ADC_handle
- 针对ADC器件AD9226的数据采集处理流程，针对手册时序做的有效数据输出控制。Verilog HDL- ADC AD9226 data acquisition device for processing flow for the manual timing do valid data output control.Verilog HDL
decode
- 通信数据中FM0数据的解码接收，解码数据和输出同步时钟。Verilog HDL-FM0 decoding the received data in the communication data, the decoded data and outputs sync clock。Verilog HDL
32-bit-division-design-In-Verilog
- 32位除法器，基于状态机设计，使用Verilog实现-32-bit division based on state machine. Using Verilog
axis_fifo
- VIVADO下使用verilog编码的axi fifo的简单使用，仿真通过，供初学者学习。-Use the following VIVADO verilog coding axi fifo simple to use, through simulation, for beginners to learn.
normCORDIC_VHDL
- 用VHDL写的CORDIC算法下求距离的一个模块，经测试可用精度高-By seeking lower write VHDL distance CORDIC algorithm module, the test can be used with high precision
eup
- It is the HDL and MATLAB code for image processing in Modelsim.
TVout
- TV Output for Xilinx FPGAs
WS2812B_deneme
- WS2812B strip driver sample