资源列表
Electronic-Design-Automation-Vhdl
- 各种计数器，编码器，全加器等元件的VHDL语言描述-A variety of counters, encoders, such as full-adder components described in VHDL language
englishVHDL
- 在VHDL语言中如何使用LPM库.PPT-In the VHDL language how to use the LPM Treasury. PPT
clock
- 原创：基于VHDL语言编写的电子钟。采用模块化编写，可以调整时间，采用动态扫描显示时分秒-Original: Based on the VHDL language electronic bell. Modular prepared, you can adjust the time, dynamic scanning is displayed every minute
Fifo
- 一个FIFO源代码，基于Altera FPGA-A FIFO source code, based on Altera FPGA
usbin_v1.7
- 用于cy7c68013与fpga的从FIFO通讯.版本1.7-For the CY7C68013 and FPGA communications from the FIFO. Version 1.7
EG7014_v1.0
- 用于fpga对EG7014液晶屏的刷新显示。avalone接口。-For the FPGA on the EG7014 LCD display refresh. avalone interface.
loop
- 对锁相环路的仿真，二阶环的仿真与分析都可以通过这个文件来到完成-Simulation of PLL, second-order loop simulation and analysis can be completed by the adoption of the document came
szzh
- 在VHDL程序中,不同类型的对象不能代入,因此要进行类型转换.类型转换的方法有-In the VHDL program, different types of objects can not enter, so to conduct the type of conversion. The type of conversion methods
dds_new
- 驱动时钟加入了PLL,使得DDS的驱动时钟可变.32位的NCO使得DDS的分辨率可以做到Hz量级-Clock driver joined the PLL, the DDS makes the clock-driven variable-.32-bit NCO makes the resolution of DDS can be done Hz magnitude
yinyue
- 音乐，用vhdl编写的程序-Music, using VHDL preparation procedures
VGA_driver_verilog
- 基于Verilog HDL的VGA驱动程序设计-Based on Verilog HDL design of the VGA driver
led_display
- 基于Verilog HDL的流水灯程序设计-Verilog HDL-based design flow lights