资源列表
2
- VHDL代码，一些课本的小程序。包含3线-8线译码器，4选1选择器，6层电梯，8线-3线编码器，8线-3线优先编码器，8选1，BCD-7段显示译码器真值表，半加器，摩尔状态机，数字时钟，序列检测器的设计，一般状态机等等。(VHDL code, some textbooks for small programs. It includes 3 line -8 line decoder, 4 selector 1 selector, 6 elevator, 8 line -3 encoder, 8 l
project.map
- D Flip Flop for Single Bit Store
Icarus-master
- Icarus bitcoin fpga code for ZTEX
uart
- uart串口FPGA实现示例 example(uart serial interface example)
random_check
- 随机码流中的报文捕捉器，Verilog编写，本报文捕捉器用于记录报文中数字信号“1”的个数。当报文捕捉器检测到随机码流中出现“1101”的序列后，确认为报头，并开始对后续正式报文中的“1”进行计数，针对AX516系统开发板(A message trap in a random stream, written by Verilog, is used to record the number of "1" in a message. When the packet capture
26518282FPGA
- ep2c20f484n的应用，具有很大的作用(The application of ep2c20f484n has a great effect)
55680576lift
- 电梯的智能控，是很好的毕业设计选择，十分有用(The intelligent control of the elevator is a good choice of graduation design)
1
- curcuit simulation in Hspice
数字钟
- 数字钟(Digital clock)
DDS的VERILOG原代码
- 实现了DDS的verilog源代码，可以使用(ajhsjdhjkshfjhfsjkjksa)
20180125_5M_01
- 基于verilog产生伪随机二进制序列，序列速率为5M(A pseudo-random binary sequence based on verilog.)
LS165
- LS165移位寄存器的verilog语言编写(The writing of the Verilog language of LS165 shift register)