资源列表
8. FILTER
- DIGITAL FILTER GUI matlab
5.44业务配置
- 是一种常用的router acl配置，就是一种常用的router acl配置(It's a common router ACL configuration, a common router ACL configuration)
BluetoothApis
- dsaf,sdv,fsdj,hva,dj lbw,jbwdhv,bjOFVUOVWHCJVB,ohjvcadshjvah,xvhasvah,vcsdhck(dsv,dsjhdfasd,daokhvapHFUWP,FDKAJNDBVHIIHCNDSJ,sandiwv)
an495_design_example
- ALTERA ers that having account in so they can help you to get your files. But to prevent overloading and abusing; We have some.ers that having account in so they can help you to get your files. But to prevent overloading and abusing; We have some.
an496_design_example
- MAX II that having account in so they can help you to get your files. But to prevent overloading and abusing; We have some. ers that having account in so they can help you to get your files. But to prevent overloading and abusing; We have some.
Greedy_snake
- 贪吃蛇，用SPARTAN6系列FPGA实现的贪吃蛇例程，用ISE14.7打开即可，Verilog语言(greedy_snake.rar The realization of the snake in the Verilog language Using ISE14.7)
51CTO下载-VerilogHDL程序设计实例详解12
- VerilogHDL 程序设计实例详解(VerilogHDL program design example detailed solution)
2mw PMSG Complete data
- ndbnfbwfnbbfwhdbfhhwdbhfhbhdhsfbubhb
Mashayan
- rebuild file in check for
hdlsrc
- cONVERTER FROM MAT TO HDL
UART
- 本人用verilog编写的UART协议，经测试可用。(I am prepared to use verilog UART protocol, the test is available.)
S02_CH02_MIO
- xilinx zynq的mio口测试工程，内容很详细(zynq mio test,about zynq mio pin test,very useful)