资源列表
CAN_verilog.tar
- CAN 2.0协议控制器，非常全面的控制器Verilog代码，可靠通信，可放心使用。(CAN Bus 2.0 Controller.)
xyj
- 实现洗衣机六个状态的转换，计时、报警功能。(The realization of the conversion, timing and alarm function of the six states of the washing machine.)
CH14_RGMII_UDP_TEST
- 用xilinx的SPARTAN6 实现的UDP，可通过PC机网络抓包工具进行发送和接收，增加了网络视频传输的接口，具有很好的参考价值(With the Xilinx implementation of the SPARTAN6 UDP, can be sent and received through PC network capture tools, increase the network video transmission interface, has a good reference
adv7123
- adv7123是常用的视频解码器，常常可用fpga编程控制，使其输出ntsc、pal制式，或者vga显示，这里面全是关于这方面的论文，很值得借鉴参考。(Adv7123 is a commonly used video decoder. It can often be controlled by FPGA programming, so that it can output NTSC, PAL format or VGA display, which is all about the papers
FSK调制解调
- 用Verilog语言 在 Quarters 平台 实现FSK调制与解调(The realization of FSK modulation and demodulation on the Quarters platform in Verilog language)
kdtree-scala-master
- Kd tree implementation in scala spark language
fenpin4
- 使用fpga实现四分频，将单一频率信号的频率降低为原来的1/4。(Using FPGA to achieve four frequency division, the frequency of a single frequency signal is reduced to the original 1/4.)
fft2_core
- 两点的fft实现及仿真 基于altera公司的cycloneⅣ(The FFT implementation and Simulation of two points are based on the cyclone IV of Altera company)
DDR3_controler
- s6和k7 fpga的ddr3 ip控制器使用说明；(S6 and K7 FPGA DDR3 IP controller use instructions)
uart_test
- 用verilog实现的一款232协议的源码，支持光纤传输，IO通道传输等等传输方式。(Verilog implementation of a 232 protocol source code, support fiber transmission, IO channel transmission and so on transmission.)
bist pattern generator
- document of bist with low power generator
gtx_aurora_zc706_clock_module
- 对aurora模块时钟处理模块，实现时钟的分频等处理(Aurora module clock processing module,Clock frequency division and other processing)