资源列表
Chpt04 Example Files
- testbook for vhdl coding
GCD calculator
- gcd calculator is a module that if two parameter has egual value ...
clok count and reset
- counting0 amount of pulses with reset
328 ROM module
- 32 byte ro0n moudule implementation in vhdl code
a simple 4_4 RAM module
- a simple 4*4 RAM module implementing in vhdl
simple FSM0
- simple implemenation of FSM in VHDL
ALU_4bit
- 4-bit ALU in verilog
ADC_16bit
- adc 16b thi no la nhu vay do
code
- adder 18b trong chuong trinh verilog
clock_matrix_rg
- the hien tinh cam cua nhan loai
uart_test
- 通过FPGA，实现串口传输数据，并且可以支持多种不同的波特率，用EP4CE22F17芯片实现。(Through the FPGA, serial transmission data, and can support a variety of baud rates, using EP4CE22F17 chip implementation.)
Buzzer
- 采用verilo语言编写的蜂鸣器，可用ISE软件来试实现(Buzzer written in verilo language, available ISE software to try to achieve)