资源列表
dttrytwo
- 电梯控制器，可以实现多人多楼层上下的,用的verilog，板子basys2-elevator controller
Lab4
- 该实验室会议的目的是要实现一个可配置的FM-AM数字调制器的数据通路。它是由一个CIC内插滤波器及可配置的FM-AM块。调制器信号以48kHz被取样，并且由CIC内插滤波器的装置内插高达96MHz的。在FM-AM配置块适用于96 MHz的时钟-The aim of this laboratory session is to implement the data-path of a configurable FM-AM digital modulator. It is composed of
plano
- 电子琴，手动弹奏模块，可发低八度，中八度，和高八度-Flower, hand playing modules can be made low octave, the octave and octave
CCD_frequency_generator
- CCD工业相机六路频率发生器，VHDL语言实现，非Verilog HDL-CCD industrial camera image capture six-way frequency generator, VHDL language, non Verilog HDL.
Frequency_Check
- 频率计 用于频率的测量 包括三个模块-Frequency check ,it is used to ferquency checking, and it contained three parts.
vcoPanalog_filter
- a verilog-ams code for a vco and an analog filter
test_verilog---Copie
- a verilog-ams code for a p-a verilog-ams code for a pll
d2a_a2d
- a verilog-ams code for an ADC and DAC
crc16_demo_20160425_512Byte
- 并行输入任意字节，两种国际标准的CRC16，循环冗余校验，生成多项式为8005或者1202两种国标，生成并行16为校验码，准确适用，亲测工程应用-Enter any byte parallel two international standard CRC16, cyclic redundancy check generator polynomial for the 8005 or 1202 two kinds GB, 16 generate parallel code verification,
VGA_caidai_zifu_juxing
- verilog实现VGA显示的代码，包括驱动，时钟管理，显示的全部，代码中包括三个实例，一个最常见的八个彩带型，一个矩形框，一个魔幻彩带显示实现，全部代码实现。-verilog implementation code VGA display, including the driver, clock management, all of the code displayed include three instances, one of the most common type of eight
Code1
- 拥有提前判断，和假设分支条件不满足的流水线CPU- Pipeline CPU with forwarding and predict-not-taken
lcd1602
- 在Quartus II 中用Verilog语言编写的1602英文显示程序-n the Quartus II Verilog language with English display program 1602