资源列表
AudioSubSystemStereo
- DE2-115 AUDIOSUBSSTEM
FIR_OVER
- 基于FPGA的FIR滤波器的设计，包括每个模块的设计和顶层原理图。-FIR filter design based on FPGA, including the design and top-level schematic of each module.
spram
- vhdl code of single port ram
dpram
- vhdl code dual port map
chirp
- VHDL CODE Of chirp counter
reg16
- vhdl code of 16 bit register which has 8 bit input and 16 bit output at second count-vhdl code of 16 bit register which has 8 bit input and 16 bit output at second count
universal
- vhdl code of universal shift register which o/p is control by mode input
24bitdivderVerilog
- FPGA 24位除法器编程,verilogHDL编程-The 24 bit divder used in FPGA，programmed in verilog HDL.
vga
- VGA project for DE0-nano
conv
- Convolution using VHDL (pls don try this)
Ch
- design of cache to remove tag bits
manfm
- Manchesteer-FM0 coding using verilog