资源列表
VHDL
- VHDL的4bit*4bit的有符号无符号的乘法除法实现-VHDL unsigned signed to achieve the multiplication division
aes_-vhdl
- aes encription coding in vhdl language
CDMA_DECODING
- CDMA encoding using VHDL
yingyuzimuxianshi
- 用VHDL语言编写的英语字母显示电路，经过验证-VHDL language with the English alphabet display circuit, proven
Clover_VgaCvt
- cpmposite to VGA converter c-source code
multiplier
- 几种verilog乘法器的代码，用于比较不同乘法器特点-Several multiplier verilog code, used to compare the different characteristics of the multiplier
sqrt
- FPGA的一个IP内核，用来优化除法算法的源代码包。-An FPGA IP cores to optimize the division algorithm source code package.
sdram_me
- 用verilog代码控制sdram,sdram_module是顶层模块。控制8M x 16bits x4Banks sdram. -use verilog program to control the sdram
fsks-vhdl
- 基于fpga的fsk调制解调，充分利用数字器件的数字特性。-The fsk fpga-based modem, the number of full use of digital devices characteristics.
manchester_verilog
- 这时manchesite编码，VERILOG语言，VHDL的找本站我发的帖子-manchesite time coding, VERILOG language, VHDL I find a site in a posting
Huffman
- 用VHDL编写的huffman编码的源程序-With the VHDL source code written in huffman coding
FILTER
- 一个工作频率（采样频率）100M的，截止频率10M的FIR滤波器，一共是108阶。 一共四个文件，滤波器的实现文件FILTER.v，测试平台FILTER_TB，matlab生成测试向量，和matlab读取输出数据分析。 经过了测试，是可用的-A working frequency (sampling frequency) 100M, cutoff frequency 10M FIR filter, a total of 108 bands. A total of four documen