资源列表
miaobiao
- 用VHDL语言实现对FPGA的程序编写，实现秒表功能。-Using VHDL FPGA program written stopwatch function.
assg-5-(serial-bit-adder)
- 4 bit adder using four full adder’s structural modeling style
assg-8-(barrel-shifter)-final
- Barrel shifter IN VHLD , using structural modelling
assg-2-2-code-converter
- CODE CONVERTER IN VHLD ,Binary to Gray using structural modelling of XOR Gate
uC_interface
- IIC总线微控制器的接口RTL代码（verilog）-the verilog code of IIC Uc_interface
doorlock.rar
- 门锁 状态机 verilog 适用于digilent NEXYS2开发板,doorlock state machine verilog applied to digilent NEXYS2 board
gps_code_gene
- GPS信号C/A码生成器，能够实现gps接收机中c/a码的剥离。-GPS signal C/A code generator is able to achieve a GPS receiver C/code peeled.
uart
- UART模块的verilog代码，经过测试，能够实现正常的接收和发送功能。-Verilog code for UART module has been tested, it is able to achieve normal receive and transmit functions.
Quartus10.0pojie
- licence.dat证书，用于quartus10.0的破解文件-licence.dat certificate for quartus10.0 the crack file
clock
- 一种新的时钟设计程序，有助于新手学习，完整版-A new clock design program, help novices learn the full version
SPI_FPGA_WITH_MCU
- MCU与FPGA之间实现SPI通信，包括底层的设置，按键的控制等。-SPI communication between the MCU and FPGA, including the underlying set button control.
AHB
- AMBA - AHB MASTER VERILOG CODE (UNCHECKED)