资源列表
4bit-adder
- 4 FIT ADDER FULL EXAMPLE IN VHDL LANGUAGE
RUILI
- 均匀相位的瑞利衰落信道matlab仿真程序，并附有详细注释-Uniform phase Rayleigh fading channel matlab simulation program, together with detailed notes
examples
- Examples of registers, counters, etc. on VHDL
manchester_verilog
- This design is targeted to the XCR3064XL-7VQ100C CoolRunner CPLD. This is a 3V, 64 macrocell device in a 100 VQFP package. The fitter was allowed to pick the pin-out for the device.
ahb
- 基于AMBA2.0的AHB 总线，包括arbiter，decoder，Muxs2m,Muxm2s-Based AMBA2.0 the AHB bus, including the arbiter, decoder, Muxs2m, Muxm2s
modedetct
- 功能强大的视频输入信号的模式识别verilog代码。可以综合，希望对大家有帮助-Powerful video input signal pattern recognition verilog code. Can be integrated, we hope to
uart-code-Verilog
- uart控制器源码-verilog 含源码，测试向量-uart-controller-verilog-code
h_adder
- 一种半加器的算法，是基于VHDL软件仿真。请大家下载参考！-A full-adder algorithm is based on the VHDL software emulation. Please download the reference!
DWC_mctl_ddr_fifo
- ASIC设计中各种同步异步的FIFO实现的verilog source code, 参数可配置 -almost all kinds of FIFO with verilog source code, parametes configuration
rd1014
- SDRAM控制器,对SDRAM进行页写和对SDRAM进行页读的快速读写。是一个很好的SDRAM控制器-SDRAM controller, SDRAM to write for pages and pages of SDRAM for fast reading literacy. It is a very good SDRAM Controller
SerMod
- 串口控制器，带双FIFO非常好控制 verilog-Serial controller, with pairs of FIFO very good control of verilog
dianticontrol
- 此源码为基于VERILOG的FPGA的电梯控制程序。-This source of FPGA-based VERILOG elevator control procedures.