资源列表
VHDL学习的好资料--18个VHDL实验源代码
- 20个VHDL实验源代码,包括： 1 交通灯控制器 2 格雷码变换器 3 BCD码加法器 4 四位全加器 5 四人抢答器 6 4位并行乘法器 9 步长可变加减计数器 10 可控脉冲发生器 11 正负脉宽数控信源 12 序列检测器 13 4位流水乘法器 14 出租车计费器 15 多功能数字钟 16 多功能数字秒表 17 频率计 18 七人表决器 19 数码锁 20 VGA彩条发生器
armandas-Plong-v1.0-0-g4ccefeb
- fpga protityping is a very interressant document
timer
- 基于VHDL语言的一个简单秒表，包含按键消抖模块、数码管译码、计时器等模块。直接适用于basys2和nexys3两个开发板。更改ucf文件后适用于其他开发板-A simple stopwatch based on VHDL, including key debounce module, digital decoder, timers and other modules. Directly applicable to basys2 and nexys3 two development boards
VHDL-ASK-MODULATE-AND-DEMODULATE
- 基于VHDL的ASK调制与解调设计与实现-ASK modulation and demodulation VHDL Design and Implementation
substractor
- VHDL code for full substractor
dianziqin
- EDA技术与VHDL语言课程设计，简易电子琴-EDA technology and VHDL language curriculum design
Hamming
- Hamming Encoder of 7bit in VHDL, Where it consists 3 parity bits and 4 data bits, then after it is being passed to decoder where it corrects, if their is any error and gives desired data as output. -Hamming Encoder of 7bit in VHDL, Where it consist
1602LCD-Mobile-Display
- LCD1602 通过标准程序动态显示字符 显示光标和光标闪烁打开效果 -Name: LCD1602 content: The standard procedure for dynamic display of character and the cursor blinking cursor open results
fpgajiekou
- 介绍乐关于fpga一些使用例子，对fpga的一些开发和使用做乐介绍，-Fpga some introduction about the use of music examples, some of the fpga to do the development and use of music, the
Synthesizable_FIFO_verilog
- Synthesizable FIFO Model This example describes a synthesizable implementation of a FIFO. The FIFO depth and FIFO width in bits can be modified by simply changing the value of two parameters, `FWIDTH and `FDEPTH. For this example, the FIFO depth is
using-LCD-display-welcome-to-china
- LCD循环右移显示Welcome to China-using LCD display welcome to china
AES
- AES算法加解密过程的Verilog代码，包括测试文件，通过FPGA验证。-AES algorithm encryption and decryption process Verilog code, including test files through the FPGA verification.