资源列表
shuzizhong
- 基于vhdl的数字钟完整工程文件，已在实验箱上实现-vhdl clock
alarm_clock
- digital clock with alarm and control
bijiaoqi
- 比较器，含有仿真波形，是万能的比较器，有底层模块和顶层模块-comparor
arlut_fifo_interface
- fifo控制器，可以加到nios系统下，通过nios进行FIFO的读写，经过本人的项目验证-fifo controller, can be added to the nios system, through the nios to FIFO read and write, after I verified the project
DM9000A
- Verilog 编写的网卡DM9000A的IP核，altera公司寄的DE2系统中的源程序核
ccpu
- 这个是用VERILOG做的一个8位功能很弱的CPU-this is a done VERILOG eight functional weak CPU
LCD1602
- 液晶在单片机中的显示的详细程序，已通过测试，可直接调用-In single-chip liquid crystal display of detailed procedures, has been tested, can be called directly
ddr2_model
- 从软件中自动生成的ddr2代码，是DDR2必不可少的 -Ddr2 code ~
fibonacci
- source vhdl code implement Fibonacci series in hw
shixian_of_UART
- 串口控制器的FPGA实现,用Verilog语言编写!-Serial controller FPGA, Verilog language!
bluetooth
- ip核，蓝牙bluetooth的fpga硬件实现
PAL_TV_VGA
- 基于fpga de2平台pal制式tv实现-Pal standard platform based on fpga de2 tv realization