资源列表
fpmul
- floatinfg point multiplier 32 bit parellel processing
cf.rar
- 乘法器功能 直接实现两个数字信号的相乘～,Multiplier features two digital signal direct implementation of the multiplication ~
code
- 浙江大学体系结构实验代码 实现流水线的forwarding-Architecture, Zhejiang University Experimental code pipeline forwarding
Part-2-DWT-haar-using-VHDL
- 运用VHDL语言对haar小波变换进行变换的其他程序。-Using VHDL language haar wavelet transform other program transformation.
Compare_4bit_74hc85
- ACTEL FPGA 74HC85实例演示，Verilog描述-ACTEL FPGA 74HC85 examples demonstrate, Verilog descr iption
math_real
- in this code very useful for designing real number concept
clock-domain-crossinng.pdf.docx
- this source verilog code for clock domain crossing. -this is source verilog code for clock domain crossing.
VHDLgames
- 基于vhdl的一种简单游戏设计，适合初学者，激发对vhdl编程的兴趣-VHDL based on a simple game design, suitable for beginners, excited the interest of the VHDL Programming
utopia
- utopia，system verilog写的CPU测试平台代码-utopia, system verilog code written in CPU test platform
UART
- 本人觉得还不错的vhdl写的UART程序，验证过。-I feel pretty good vhdl write UART program verified.
halfsubtracter
- this the vhdl code for half substractor gate with rtl view and simulations-this is the vhdl code for half substractor gate with rtl view and simulations
verilog_calculator
- 用verilog编写的简易计算器代码。通过一位全加器组成电路，可以实现加法、减法和乘法，并在七段数码管上显示出十进制的结果。-Simple calculator with code written in verilog. Composed by a full adder circuit, can add, subtract and multiply, and in the seven-segment LED display on the decimal result.