资源列表
pipelined_computer
- 基于de2-board的汇编以及verilog的五段流水线CPU代码，适合新手学习-Based on the de2-board assembler, and the five-stage pipelined CPU verilog code, suitable for novice learning
Verilog-HDL-chuanbing
- 用Verilog HDL语言实现并串、串并接口的转换-Using Verilog HDL and string, string, and interface conversion
FPGA-zouxiangshijie
- 从零开始走进FPGA的世界，让你受益匪浅-Scratch into the FPGA world, so you benefit
verilog-hdljingyanji
- verilog,hdl经验集，讲得很好的-verilog, hdl experience set, put it very well
Verilog--shili
- Verilog实例讲解，很好的东西-Verilog examples to explain the good stuff! ! ! !
FPGAsixaong2
- FPGA重要设计思想及工程应用之时序及同步设计-FPGA the important design thinking and engineering applications of timing and synchronization design
FPGA-sixiang
- FPGA重要设计思想及工程应用之模块化设计-FPGA design and engineering application of modular design
a-simple-state-machine
- 简易状态机 verilog实现的简单状态机，全工程不错的 典型历程 值得学习入门很好的实验例程-Simple state machine verilog achieve a simple state machine, the typical course of the whole works good deserves learning entry good experimental routines
lab1
- F:\FPGA\Spartan 3E开发板的实验例程-开发板实验例程-F: \ the FPGA \ Spartan 3E development board test routines- development board test routines
lcd12864
- LCD12864 在Spartan-3E实现教程和代码-The LCD12864 in Spartan-3E achieve tutorials and code
UFTtest
- 基于fpga的verilog写的MAX2的ufm模块使用实例-Module uses examples based on the fpga' s verilog wrote the MAX2 the ufm
uartverilog
- 基于fpga的verilog写的uart串口通信实验-Based fpga the verilog write uart serial communication experiment