资源列表
assigment3
- Construct VHDL models for 74-139 dual 2-to-4-line decoders using three descr iption styles, i.e., behavioral, dataflow and structural descr iptions. Synthesize and simulate these models respectively in the environment of Xilinx ISE with the Mod
AlteraPFPGA_CPLD
- FPGA和CPLD的学习资料，从初级到高级，从基础到深入，对于学习FPGA的初学者很有用处。-FPGA and CPLD learning materials, from beginner to advanced, from basic to in-depth for beginners learning FPGA useful.
VHDL-Binary-counter
- Binary counter, its used to count the numbers in binary format
mimasuo
- 在cpld上利用可编程逻辑器件制作一个具有密码设置，修改识别的电子密码所，代码经实验验证。-Setting a password on the use of programmable logic devices produced in cpld modify recognition by electronic password code by experimental verification.
niosflash
- nios ii flash read&write示例源代码
sqrt
- VERILOG描述的开平方模块核，开方运算是FPGA或ASIC设计中所需要的核心运算模块。-VERILOG descr iption of open square modules nuclear root operation is the core computing module FPGA or ASIC design.
divider
- VERILOG编写的24位除法器代码核，是FPGA或者ASIC设计中的一核心计算模块。-VERILOG written 24 divider code nuclear FPGA or ASIC design in a core module.
fft16
- 256点的FFT/IFFT变换VERILOG代码核。-256-point FFT/IFFT transform VERILOG code that nuclear.
ml510_bsb1_design_ppc440
- Xilinx FPGA，ML510板设计的PowerPC代码，并有相应的C设计参考-Xilinx FPGAs The ML510 board design PowerPC code, and the corresponding C design reference
sARM01_07_12_2
- verilog hdl实现的ARM处理器-ARM processor implement by verilog HDL
newpingpongf16
- verilog pingpongf16 在DE2_70开发板上实现pingpongf16 VGA显示功能，Verilog HDL编写-verilog pingpongf16 DE2_70 pingpongf16 VGA Verilog HDL
decoder38
- verilog 在DE2_70开发板上实现38译码器功能电路，Verilog HDL 语言编写-verilog DE2_70 38decoder Verilog HDL