资源列表
develop_frame_find
- 基于FPGA中OFDM中的帧检测，由于采用简化算法，采用较少的复数乘法器，易于硬件实现，且节省资源，采用verilog实现.-Frame detection based on FPGA for OFDM, a simplified algorithm, using less complex multiplier, easily implemented in hardware, and save resources, the SNR performance is slightly lower th
video_systems.tar
- H264 decoder on Stratix VI-H264 decoder
Project
- 通过动手实践，熟悉Altera基本宏功能的产生和实现方法-Incurred and realized by hands familiar with Altera Basic macro functions
uart_regs
- 通过动手实践，熟悉使用Quartus II设计FPGA的方法-By hands-on practice, familiar with the method of using Quartus II design FPGA
rc_flt
- 基于FPGA实现的64阶升余弦FIR并行滤波器，采用iso18000.6c标准实现，具有很好的低通滤波效果，已通过后仿上板验证，采用verilog语言实现。-64 order raised cosine FIR FPGA-based parallel filters, implemented using iso18000.6c standard with a low-pass filtering effect imitation on the board has passed validatio
HalfbandDec
- 基于FPGA开发的11阶半带升余弦FIR滤波器，用在阅读器基带滤波时的抽取滤波器使用，采用verilog语言实现。-Raised cosine FIR filter based FPGA development 11 order of half-band decimation filter used in reader baseband filtering, using verilog language implementation.
Function_clock_generate
- 基于FPGA实现的实时闹钟，在DE2—115开发板上通过验证，实现报时，定时，时间调整等功能-Based on verified DE2-115 development board FPGA to achieve real-time alarm, timekeeping, timing, time adjustment
Autoseller_verilog
- 基于FPGA实现的自动售货机，采用verilog语言实现-Vending machines based on FPGA verilog language
Chinese_music_play
- 基于FPGA实现开发的中国古曲《高山流水》蜂鸣音乐，采用verilog实现。-" Mountain and Flowing Water" beep music based on the classic Chinese music FPGA implementation developed using verilog achieve.
AsgPart4
- verilog prormmaing language exercises, introduction-verilog prormmaing language exercises, introduction
leda
- 实现1：LED流水灯A 实现了可控的LED跑马灯-Achieve 1: LED light water A controllable LED Marquee
digital-clock-use-lcd
- 使用飓风2号试验板,利用液晶显示星期，数码管显示时间-use cyclone2 board,use lcd to show the week,use seg to show the time