资源列表
Visio-绘图21
- 这是asic流程例子.文件内容已经验证过.如有疑问和我联系-This is the process blends example. The contents of the documents has been proven. And I doubt if links
LCDshow
- 基于VHDL的LCD显示程序,包含完整的源代码,锁脚文件以及下载文件,可直接下载使用
divise-frequent
- 分频器FPGA代码设计，可将高频分为任意频率的低频-Divider FPGA code design can be divided into any high-frequency low-frequency
vhdl
- 本程序是基于FPGA的单片机的高效实现，用的是vhdl语言实现的-This procedure is based on efficient single-chip FPGA using VHDL language
Quartus2-superLicense
- 万能Lisence,本许可适用于各个版本的Quartus
shumaguan
- 数码管显示，一种很好的数码管显示方法，很简单-Digital display, digital display method for a good, simple
fifo
- 使用Verilog语言编写，把FPGA配置成一个fifo
CC2530-UART2TEST
- descr iption：CC2520UART1-TX&RX-RECEIVE AND TRANSIT
aurora_ipcore_dir
- xilinx v5下面，一个基于aurora通信的实现代码-implement of aurora in xilinx
entropy_coding
- 用verilog 描述的嫡编码(entropy coding) 应用于图像压缩编码 有测试文档 -using Verilog His descr iption of coding (entropy coding) for image compression test files are encoded
FIR64tap
- 使用verilog语言实现64阶FIR,调试可以通过-64 taps FIR with verilog
alu8bit4fun
- its a 8 bit arithmetic nd logical code in verilog it is used for 4 different functions.