资源列表
generic_fifos_latest.tar
- fifo的verilog代码，包含rtl，sim，testbench内容的verilog代码，完全可用-rtl code of a fifo
mem32_to_pcitarget_verilog
- This design example shows how to implement interface between 32-bit pci target Altera megafunction instantiation and a 32-bit synchronous memory
miniUart
- 一个简单的uart的VHDL描述，希望对大家有点帮助-A simple UART in VHDL descr iption, I hope all of you a little help
xc9500xlIBIS
- XC9500XL CPLD IBIS Model
bitdetect
- verilog代码编写110100序列的序列检测器，用状态机实现，包括仿真测试代码-verilog coding sequence detector 110100 sequence state machine implementation, including simulation test code
thirty_VHDL_coder
- 三十个vhdl源码，对于刚开始学习vhdl的很有帮助，可以帮助理解数字电路-30 vhdl source for the beginning of the study vhdl helpful, and can help to understand digital circuit
cordicsg
- Xilinx system generator design of CORDIC
SDcardcode
- 基于c语言上的SD卡读写源程序，希望对大家有所帮助~
51_FPGA
- 51单片机与FPGA之间通讯，FPGA扩展出通讯端口-51 communication between the MCU and FPGA, FPGA expansion of the communication port
rtl
- LCD1602 Verilog 代码实现。包括数据读写，地址读写，初始化。支持4位总线格式。注意:此程序已经在ML506板子上验证过。本人花了好几天调试，开发出来的。值得推荐。-Verilog coding for LCD1602 display
alarm
- 闹钟设计，VHDL，源代码。 -Alarm clock design, VHDL, the source code.
exp8
- 8051, microcontroller beased design