资源列表
7-BCD
- 7段数码管控制接口程序和对初始频率为50MHZ的时钟的分频程序-7-segment control interface program and the initial frequency of 50MHZ clock divider program
shockware
- VHDL 波形防止抖动程序,学习试验材料-VHDL prevent jitter waveform procedures, the pilot study materials
config_ad6636
- 用Verilog正确配置ad6636，，在ISE环境中正确编译与实现-Properly configured with the Verilog ad6636,, compiled in the ISE environment and realization of the right
fadder
- 利用两个半加器来组成的全加器，是简单的vhdl语言入门-The use of two and a half adder to form the full adder is a simple entry-vhdl language
ScanKey
- 在FPGA中用verilog编写的键盘扫描程序，返回时有中断-the program write by verilong which use to scan the switch and return inturrupt in fpga.
ad0809
- ADC0809 verilog-ADC0809 verilog...............................
ram_dp_sr_sw
- dual ram port in verilog
bayer_sensor_mod
- 基于verilog编写的 CMOS sensor 模型，可以输出bayer 数据，尺寸可调-Verilog prepared by the CMOS sensor model, you can output bayer data, size adjustable
Filter_Convolution_Example
- Example of a convolution filter implemented in Vivado HLS, the high level synthesis tool Xilinx-Example of a convolution filter implemented in Vivado HLS, the high level synthesis tool Xilinx
signal-generator
- FPGA 信号发生器的程序，在实验板上调试成功
shift_register
- -- DEscr iptION : Shift register -- Type : univ -- Width : 4 -- Shift direction: right/left (right active high) -- -- CLK active : high -- CLR active : high -- CLR type : synchronous -- SET active : high -- SET type : synchronous
trafficlight
- design and simulate the traffic light controller-design and simulate the traffic light controller