资源列表
tb_Moteur_test
- Test Bench for an engine code VHDL for CY7C1062AV-Test Bench for an engine code VHDL for CY7C1062AV33
sumUnit
- 包含一个将二进制加法结果转换为3位BCD码的结构。以方便用七段译码器显示结果。-Convert result of binary adding to 3-digits BCD code, and thus make it easy to display the result with 7 segments decoders.
test_led
- 数码管点阵实验，在上显示数字0到9，测试点阵的功能。-Digital tube lattice experiment, shown on figure 0-9, test the function of the lattice.
instmemory
- Instruction memory in VHDL
uart_rx
- Universal Asyncronos Received Transmitter
complex_mult
- Complex mult in vhdl
cordic
- CORDIC algorithm VHDL FPGA
shape
- 实现梯形滤波，对于输入为指数函数的类型。希望能够对你有帮助-tixing filter。hoping it will do help to you.
Analog-to-digital-converter
- 模数转化器，64位双精度的模拟输入值，16位数字输出-Analog to digital converter, 64-bit double-precision analog inputs, 16 digital outputs
shift_detector
- shift detector for altera
ram_dp_sr_sw.v
- this is a verilog source code for Dual Port RAM Synchronous Read/Write.
miaobiao
- verilog 的 48M频 出入秒表，带停止启动 清零功能-the verilog of 48M frequency of access stopwatch, with stop start clearing the