资源列表
j_k
- jk counter using verilog
textfilereading2
- It is a VHDL code for the operation of file reading by IEEE commands which can transfer the multiplr data
cpld1380
- 一个很好的VHDL实现的功能模块程序,希望你可以用的上!-a good VHDL functional module procedures in the hope that you can use!
DEBOUNCE
- 一个小程序,弹跳消除电路,可消除按健的毛刺干扰-a small procedure, bouncing elimination circuit, according to remove the burr-interference
MatchFilter
- Quartus Ⅱ开发环境，VHDL语言实现扩频通信的匹配滤波功能。用于匹配滤波器的FPGA实现！
zzripple_carry_mult
- 乘法实现利用verilog语言,经过仿真验证,功能正确无误.适用于初学者反复研究练习
choosebcd
- 基于vhdl的BCD码转ASCII码的设计，已经经过调试，可直接使用-Vhdl code based on the BCD to ASCII code of the design, debugging has been directly used
butterfly1
- FFT 蝶形处理器的VHDL代码，由一个加法器，一个减法器和一个实例化为组件的旋转因子乘法器ccmul组成-FFT butterfly processor VHDL code by an adder, a subtracter, and an instance of the component into the composition of the rotation factor multiplier ccmul
SIG_1KHz
- 任意移相方波信号产生的VHDL代码。输入任意一个的相位偏移值就都能产生与参考方波有指定相位差的同频信号。-Square-wave signal of arbitrary phase shift generated by VHDL code. Enter any one of the phase offset can be generated on a designated phase with the reference square wave signal the same frequency
RAM_module
- file contain vhdl code for RAM module
vhdl
- 4位乘法器 vhdl library IEEE use IEEE.std_logic_1164.all entity one_bit_adder is port ( A: in STD_LOGIC B: in STD_LOGIC C_in: in STD_LOGIC S: out STD_LOGIC C_out: out STD_LOGIC ) end one_bit_adder -4-bit multipl
parallel-to-serial-conversion
- 该模块实现的是并串转换功能，经过仿真验证没有问题-This module is designed to implement parallel to serial conversion